This application is based on applications Nos. 11-060441, 11-064388, 11-066451, 11-073181, 11-081218, 11-085210 and 11-357320 filed in Japan, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to direct memory access control (referred to as DMA control hereinafter). More particularly, the present invention relates to a direct memory access controller which can appropriately reconcile pluralities of memory access made by a plurality of devices connected to a common bus in accordance with operation state of the devices. For example, such a DMA controller is applicable to a copier wherein CPU and other devices such as scanner and printer share a bus.
2. Description of the Prior Art
There has conventionally been known a DMA controller including a bus-use reconcilement section for reconciling pluralities of bus-access based on bus-access requests generated from a plurality of devices. FIG. 48 shows an example of a conventional DMA control system. Basically, the system shown in FIG. 48 includes a memory 107, DMA control sections 101, 102, 103, and an access control section 104. In the conventional system, the DMA control sections 101 to 103 and the access control section 104 get access to the memory 107 via a common bus 105. Furthermore, the system has a bus-use reconcilement section 106 for reconciling pluralities of bus-access between the bus 105 and each of the DMA control sections 101 to 103 and the access control section 104. Still further, DMA control sections 101, 102, and 103 are connected to a printer 111, a scanner 112, a hard disk 113, respectively. The access control section 104 is connected to a CPU 114.
The conventional DMA control system works as follows. See FIG. 49. For instance, when the DMA control section 101 needs access to the bus 105, the DMA control section 101 sends a request signal req1 to the bus-use reconcilement section 106. If the request is acceptable, the bus-use reconcilement section 106 returns a bus-use permission signal ack1 in response to the req1. While the ack1 is in an active state, the printer 111 can get access to the bus 105 through the DMA control section 101. It is same for other devices connected to other DMA control sections.
When those control sections send requests concurrently, the bus-use reconcilement section 106 is designed to return bus-use permission signals to each of the requests in order based on a predetermined priority ranking. FIG. 50 shows an example of priority ranking for bus-access. In case of FIG. 50, when request signals req1, req2, req3, and req4 are generated concurrently, the bus-use reconcilement section 106 returns a bus-use permission signal ack1 only since the DMA control section 101 is assigned to the highest in the predetermined priority ranking. Thereby, the DMA control section 101 gets access to the bus 105 prior to the other control sections 102 to 104. Similarly, when request signals req2, req3, and req4 are generated concurrently, the bus-use reconcilement section 106 returns a bus-use permission signal ack2 only since the DMA control section 102 is assigned to the highest among control sections 102 to 104. Therefore, the DMA control section 102 gets access to the bus 105 prior to the control sections 103 and 104.
However, since the conventional DMA controller 100 controls bus-use reconcilement in accordance with the access priority ranking shown in FIG. 50, there has been a fear that a device assigned to higher priority such as printer 101 is likely to occupy the system. Furthermore, in a case that request signals req1, req2, req3, and req4 generated at the DMA control sections 101, 102, 103, and the access control section 104, respectively, go out to the bus-use reconcilement section 106 intensively, there has been a fear that a device assigned to lower priority, such as the CPU 114, can hardly get access to the bus 105. Under such a situation, program for the system is likely to stop because the CPU 114 cannot get access to the bus 105. What is more, it has been a problem that the conventional DMA controller 100 cannot lower power consumption effectively.
The present invention is intended to solve the above-described problems of the conventional DMA controller. Its prime object is to provide a DMA controller wherein use-state of a common bus is detected with respect to a plurality of devices so that each of the devices can appropriately get access to a common bus under bus-use reconcilement control based on the detection result. Another object is to provide a DMA controller capable of lowering power consumption appropriately in response to use-sate of a common bus.
In order to achieve the above objectives, the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and bus-use reconcilement means for reconciling pluralities of bus-access made by the devices based on a detection result obtained by the bus monitor means.
The bus monitor means for the DMA controller detects use-state of the common bus with respect to each of the devices every predetermined period. Then, the bus-use reconcilement means reconciles pluralities of bus-access among each of the devices based on the detection result obtained by the bus monitor means. Thereby, pluralities of bus-access among each of the devices are appropriately reconciled in proportion to bus use rate for each of the devices. As a result, bus-occupation by a device assigned to higher priority is avoided even when devices generate requests intensively. Thereby, a device assigned to lower priority can obtain necessary access time. That is, this system enables all the devices connected to the common bus to get access to the bus appropriately. Particularly, this can surely prevent program from stopping.
For detecting use-state of the common bus, the bus monitor means may integrate generation time of bus-use permission signals output from the bus-use reconcilement means. Alternatively, the use-state of the common bus may be detected based on an in-use-state signal the common bus generates. Further, the inventive DMA controller may reject a request from at least one of the devices so as to achieve access reconcilement in accordance with the detection result obtained by the bus monitor means. Preferably, such a request rejection is given to a device assigned to higher priority ranking than a device the ranking of which should be made higher and does not need real time processing.
Thus, the inventive DMA controller changes manners of bus-use reconcilement along with use-state of the common bus with respect to each of the devices connected the bus. Thereby, problems such as that particular device occupies the common bus or, vice versa, particular device can hardly get access to the bus can be avoided.
Furthermore, the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and priority determining means for determining bus-use priority ranking for each of the devices in accordance with a detection result obtained by the bus monitor means. For this type of DMA controller, the bus-use reconcilement means may reconcile pluralities of bus-access made by each of the devices in accordance with the bus-use priority determined by the priority determining means.
In the inventive DMA controller, when the bus monitor means detects use-state of the common bus with respect to each of the devices every predetermined period, the priority determining means determines priority of the common-bus use for each of the devices in accordance with the use-state result. Following the determined priority, the bus-use reconcilement reconciles pluralities of bus-access made by the devices. Thereby, pluralities of access made by each of the devices are properly reconciled in accordance with use-state of the common bus.
For determining bus-use priority, the inventive DMA controller may include either a plurality of priority tables one of which is selected in accordance with a detection result obtained by the bus monitor means or a standard priority table which is changeable in accordance with a detection result obtained by the monitor means. As to the latter case, the standard table may be used without a change, if a detection result does not require priority-ranking change.
This DMA controller is significant in a particular case that one of the devices is a processor. In this case, it is preferable that the bus monitor means calculates bus-use rate of devices every predetermined period except for the processor. Then, in case the use-rate exceeds a predetermined value, the bus-use reconcilement means may allow the processor to get access to the common bus prior to other devices during a predetermined period.
In this DMA controller, when bus-use by a device other than the processor exceeds a predetermined value, the bus-use reconcilement means allows the processor to use the common bus prior to other devices during a predetermined period. Thereby, even if requests concentrate in a short time and bus-use rate by other devices becomes high, the processor can surely get access to the bus. Accordingly, the above system surely avoids a case such that the processor cannot get access to the common bus and stops program. A predetermined period may be set to a bus-use rate that can possibly prevent the processor from getting access to the common bus. In addition, a predetermined period of bus-use opened to the processor may be set to a maximum length of time that devices which need real time processing can await processing. This is to avoid affecting real time processing.
For achieving the above object, the bus-use reconcilement means may cancel requests from devices other than the processor when bus-use rate obtained by the bus monitor means exceeds a predetermined value.
Another aspects of the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; device monitor means for detecting operation state of each of the devices; and bus-use reconcilement means for reconciling pluralities of access to the common bus made by the devices based on a detection result obtained by the bus monitor means.
In this DMA controller, the device monitor means detects operation-state of devices connected to the common bus. Next, the bus-use reconcilement means reconciles bus-use permission in response to requests sent by each of the devices. Thereby, pluralities of bus access made by each of the devices and the processor are properly reconciled in accordance with operation-state of the devices. Operation-state mentioned herein indicates bus-access state for each of the devices, i.e., presence/absence of access.
For an access reconcilement method, the inventive DMA controller includes a plurality of different priority tables and selects one of the tables based on a detection result obtained by the device monitor means, whereby pluralities of bus-access are reconciled in accordance with a priority table selected. As another method, the DMA controller includes a plurality of different access-interval tables on which minimum bus-access time for each of the devices is recorded and selects one of the tables in accordance with a detection result obtained by the device monitor means, whereby permission/rejection of bus-access for each of the devices are determined in accordance with an access-interval table selected.
Still further, another aspect of the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; device monitor means for detecting operation state of each of the devices; and DMA-transfer-method changing means for changing DMA-transfer methods between the memory and at least one of the devices in accordance with a detection result obtained by the bus monitor means.
The bus monitor means for the inventive DMA controller detects use-state of the common bus. Then, DMA-transfer-method changing means changes DMA-transfer methods between the memory and each of the devices in accordance with a detection result obtained by the bus monitor means. Therefore, data are transferred between each of the devices and the memory in accordance with an optimum transfer method selected in accordance with use-state of the common bus. Accordingly, DMA transfer is exercised efficiently. In addition, those methods surely avoid problems such that real time processing cannot be made in time and that processing by a processor cannot be made in time.
Preferably, the bus monitor means detects operation-state of a device which needs real time processing when both data to be processed in real time and data not to be in real time are included. Furthermore, the transfer-method changing means preferably changes units of transfer-word for DMA transfer. More specifically, as for the case that real time processing is needed, DMA may be transferred by small amount of data unit and as for the case that real time processing is not needed, DMA may be transferred by large amount of data unit. Thereby, DMA is transferred significantly effectively within a range that does not affect real time processing.
Furthermore, the inventive DMA controller includes: a memory; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and mode-switch means for switching to low-power-consumption mode in accordance with a detection result obtained by the bus monitor means.
The mode-switch means for the inventive DMA controller switches operation modes from normal mode to low-power-consumption mode in accordance with a detection result obtained by the bus monitor means. Thereby, a switch to low-power-consumption mode is surely exercised when a device is in little active. Accordingly, power consumption can be lowered effectively.
The mode-switch means may be clock-decrease means for decreasing frequency of system clock. The clock-decrease means may be means for decreasing operational frequency of processor control signal when one of the devices is a processor. In case the memory includes recording means capable of writing and reading data on demand (DRAM, for example), the clock-decrease means may be means for decreasing operational frequency of control signal for the recording means. A processor control signal referred to herein indicates a control signal sent to the processor.
In case the memory is capable of writing and reading data on demand, the mode-switch means may be a manner that switches an operation mode to a self-refresh mode. Self-refresh mode herein means a mode to exercise refresh operation automatically within the recording means. In general, some commands are required for a switch between self-refresh mode and normal mode.
Further, the inventive DMA controller may include: a memory having a plurality of memory blocks; a common bus connected to the memory; a plurality of devices connected to the common bus and accessible to the memory through the common bus; bus monitor means for detecting use-state of the common bus with respect to each of the devices every predetermined period; and memory controller means for controlling operation mode of each of the memory blocks in accordance with a detection result obtained by the bus monitor means.
The bus monitor means for the inventive DMA controller detects use-state of the common bus with respect to each of the devices every predetermined period. The memory controller means controls operation mode of each of the memory blocks in accordance with a detection result obtained by the bus monitor means. Thereby, operational mode suitably capable of coping with processing speed is selected for each of the memory blocks. Accordingly, when high-speed processing is not required, operation mode switches to low power consumption mode to lower power consumption effectively.
In general, each of the memory blocks is recording means capable of writing and reading on demand, and the memory controller means sets operational mode of the recording means in any one of the three modes, namely, normal mode, power-down mode, and self-refresh mode. Power-down mode and self-refresh mode lower power consumption much more than normal mode (about 1/50).